In many data processor applications, the validity of data stored in a particular memory location is determined by an associated tag. Therefore, for a particular data access to be successful, the tag associated with the requested data must fulfill a predetermined criteria. External memory caches and error correcting code (hereafter simply "ECC") memory systems are two data storage mechanisms in which the validity of data is determined by such a criteria.
An external memory cache is a relatively small, high speed memory system for supplying frequently used data to a data processor or other device. The data is periodically loaded from the data processing system's slower main memory into the external memory cache when time permits and as needed by the data processing system. The data is also periodically reloaded into the main memory from the external memory cache to free external cache memory locations for other data.
An external memory cache is characterized by its location in a particular system. An external memory cache is not located on the same integrated circuit or "chip" as is the data processor or other device to which the external memory cache supplies its data. Conversely, an external memory cache is a cache system located on a data processing unit to which the cache supplies its data. The external memory cache, however, may be the only cache associated with a data processing system. An external memory cache does not require an internal memory cache system to operate successfully.
Any cache is divided into a number of memory blocks and a corresponding number of "tags." Each memory block contains data that is useful to the operation of the data processor. Each tag is associated with one or a group of the memory blocks and contains data identifying the associated memory block or group of memory blocks. Typically the tag contains data representative of a portion of the main memory address from which the associated data block was loaded. Caches can store each data block in only one or a few particular cache storage elements. The storage elements are accessed through a subset of the main memory address bits of the dam. The ability to have storage elements indexed by the same address bit subset is known as "associativity." For instance, in a four-way associative cache, each memory address may be mapped to four locations in the cache. A direct-mapped memory cache is the degenerate cache case. In a direct-mapped memory cache each memory address may only be mapped into one cache storage element.
When a data processing system requests data from an external cache, the cache must access the one or more possible locations of the data block and compare the associated tag of each with a subset of the address of the requested block. If one of the tags matches the data address, then a "hit" occurs and the associated data of that tag is forwarded to the data processing system. If none of the tags match the memory address, then a "miss" occurs and the cache must access its main memory system to acquire the requested data.
Error correcting code memory systems are memory systems used when data integrity is critical. Financial transactions are a class of data processing operations in which data integrity is critical. There, an incorrect bit in a memory block may represent millions of dollars added or subtracted. ECC memory systems operate by associating a tag with each memory block. The data within each tag is calculated by performing a function on the associated data block when the data block is first stored into memory. The function may be recalculated each time the data block is retrieved from the memory and the result compared to the stored tag. If the result and the tag differ, then a memory error has occurred. In addition, most schemes allow certain errors to be corrected as well as detected. For instance, in one ECC memory scheme each 64-bit data block has an 8-bit tag associated with it. Each tag can detect single- and doublebit errors in an associated data block and may correct single-bit errors. The memory blocks with double-bit errors produce memory access errors.
Known external caches and known ECC memory systems incur a time penalty because of each system's tag comparison relative to a memory system without a tag. Each system must retrieve the requested data, make a tag comparison and then either forward the requested data based on the tag comparison or take some remedial action. As data processing systems become faster, all types of memory systems must become faster to avoid stalling the data processing system during data load operations.